1. Field of the Invention
The present invention relates to a power gating structure, and more particularly to a power gating structure, a semiconductor device including the power gating structure and a method of controlling a power gating capable of retaining data in a low-power mode and reducing power consumption in a power-down mode.
2. Description of the Related Art
As a portable system becomes smaller and lighter, semiconductor devices applied in the portable system include a greater number of operational blocks. Power consumption of the semiconductor device should be low so that a method of cutting a power supply to inactive blocks among the included operational blocks can be effective.
In such a portable system, a data retention mode should be considered, in which an operational block does not operate but data should be retained while a power supply is cut. As a scale of semiconductor manufacturing process becomes smaller to submicron dimensions, elements in a semiconductor device become smaller and leakage current is increased. In order to reduce leakage current amounts of the elements, a method of a multi-threshold complementary metal oxide semiconductor (MTCMOS) using a plurality of metal oxide semiconductor (MOS) transistors, each having a respective threshold voltage, is applied widely in the semiconductor device. However, in the conventional method of the MTCMOS, a ground voltage can be bounced and data can not be retained due to the ground bouncing, that is, a fluctuation of a ground voltage.
FIG. 1 is a diagram illustrating a conventional power gating structure using MTCMOS transistors.
Referring to FIG. 1, the conventional power gating structure includes a plurality of logic blocks arranged between a higher power supply line VDDL and a virtual ground VGND, and a plurality of NMOS transistors that are serially coupled to the plurality of logic blocks, respectively. Each NMOS transistor is coupled between the virtual ground VGND and a ground line GNDL. The higher power supply line VDDL is coupled to a higher power supply terminal VDD through a first path modeled by a first resistor R, a first inductance L, and a first capacitance C. The ground line GNDL is coupled to a ground terminal GND through a second path modeled by a second resistor R′, a second inductance L′, and a second capacitance C′.
The NMOS transistors are turned on and off as a function of applied control signals, and the timing thereof. When t<0, a first control signal CON1 is a logic “high” and a first NMOS transistor 12 is turned on so that a first logic block 11 operates normally. In addition, when t<0, a second control signal CON2 is a logic “low” and a second logic block 13 is isolated from a power supply by a second NMOS transistor 14. When t=0, the second control signal CON2 becomes a logic “high” and the second NMOS transistor 14 is turned on so that the second logic block 13 is connected with the power supply. At that time, a voltage level of the ground line GNDL with respect to the ground terminal GND can not be maintained constant and, in fact can be bounced. The first NMOS transistor 12 is still turned on so that the voltage level of the ground line GNDL influences a virtual ground VGND1 directly. Thus, a voltage level of the virtual ground VGND1 can not be maintained constant and can also be bounced, largely so that a logic level of an output signal of the first logic block 11 can be also influenced.
A method for solving the ground bouncing is disclosed in U.S. Pat. No. 6,977,519. In the method, two control signals are applied to a power gating structure. The power gating structure is controlled by a combination of first and second control signals so that logic blocks can be operated in one of an active mode, a data retention mode, and/or a power-down mode. When an operation mode of the logic block is changed from the power-down mode to the active mode, the logic block passes through the data retention mode so that the ground bouncing can be reduced.
However, in the conventional method, only when the times of applying the control signals are matched exactly, does the logic block operate normally. For example, when the operation mode is changed from the active mode to the data retention mode, logic levels of the first and second control signals should be changed from ‘0’ and ‘0’ to ‘1’ and ‘1’ concurrently. In the power-down mode, logic levels of the first and second control signals are ‘1’ and ‘0’. Thus, when the first control signal is changed to ‘1’ previously to the second control signal, a power supply can be cut in a moment and data can be lost in the logic block. It is not easy to transfer the first and second control signals to respective components of a semiconductor device exactly at the same time.
In addition, a PMOS transistor in the conventional method is formed in an N-well of a P-substrate and thus a band-to-band tunneling BTBT can occur between an N-body that is heavily doped and a node of a P-drain. That is, leakage current can occur between the P-drain and the N-body, even in the power-down mode.